Dynamic random access memory circuitry (DRAM) is comprised of a plurality of individual memory cells. Individual cells comprise an access transistor, a capacitor and conductive access to a bit line. One source/drain region of the access transistor electrically connects with the capacitor, with the other source/drain of the access transistor electrically connecting with the bit line. Once set, the storage node of the capacitor is not able to maintain charge due to current leakage through the source/drain region to which it is connected to substrate material therebelow. Such requires charge refreshing of a charged memory cell to maintain its desired memory state. The time between the capacitor recharging is known as “refresh time” or “retention time”. One adverse phenomenon is known as “variable retention time”. Such results in the refresh time for individual DRAM capacitors varying over time, sometimes increasing and sometimes decreasing.
It is desirable to create good electrical connection between the storage node electrode of the capacitor and the source/drain region which is typically formed of conductively doped semiconductive material. One manner of doing so is to provide a metal interface between the capacitor storage node and the conductively doped semiconductive material. Such contacts significantly improve electrical connection between source/drains and capacitor storage nodes. However, such also tend to significantly increase leakage current to the underlying substrate material. One known manner of reducing such leakage current is to provide an insulative layer beneath the active area within which the source/drain regions and channel regions are formed.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.